The semiconductor industry is rapidly developing chips with smaller and smaller transistor dimensions to gain more functionality per unit area. As the dimensions of devices continue to shrink, so does the gap/space between the devices, increasing the difficulty to physically isolate the devices from one another. Filling in the high aspect ratio trenches/spaces/gaps between devices which are often irregularly shaped with high-quality dielectric materials is becoming an increasing challenge to implementation with existing methods including gapfill, hardmasks and spacer applications.
There is a need in the art for new methods for chip designs with smaller critical dimensions. Additionally, there is an ongoing need for high quality metal oxide films for hardmasks and spacer applications, as well as methods for forming patterned films on substrates.